1. Field of the Invention
This invention is in the field of packaging integrated circuit (I.C.) chips and more particularly relates to the field of packaging a plurality of I.C. chips on a substrate to form hybrid circuit packages.
2. Description of the Prior Art
I.C. chips, or dies, are generally packaged as either discrete devices, one chip per package, or as part of a multichip hybrid circuit, or hybrid package, where a plurality of I.C. chips are mounted in one such package. Each such hybrid package may be treated as a building block for complex electronic circuits and systems such as general purpose digital data processing systems.
In producing hybrid packages, an approach that lends itself to automating the process of mounting large-scale I.C. chips on a multilayer substrate involves producing flexible beam lead frames which are laminated to a strip of thin plastic material such as standard 35 mm film. The input/output (I/O) terminals on the active faces of the chips are bonded to inner lead bonding sites of the leads at the inner end of each lead of the lead frames. In order to mount such an I.C. chip on a substrate, the I.C. chips and a portion of their leads are blanked from the lead frames and from the film segments to which each frame is attached. The outer lead bonding sites of the leads attached to each I.C. chip are formed to produce a foot at the free end of each lead, the outer lead bonding site, which foot is substantially parallel to the active face of the I.C. chip but displaced so as to be substantially aligned with the bottom surface or back face of the chip. The back face of each such chip is metallized so that the back face can be soldered to a metallized chip site on the surface of the substrate simultaneously with the bonding of the outer lead sites of the leads to the outer lead pads of the substrate.
Problems associated with prior art hybrid packages having flexible beam leaded chips mounted on a fired multilayer substrate are the result of the additional manufacturing steps required to mount I.C. chips on substrates in this manner. One step is metallizing the back side of the I.C. chip, and another is the forming of the leads of the chip so that the outer bond sites of the leads will contact the I/O pads associated with each chip site of the substrate. Each additional manufacturing step increases the cost and decreases the reliability of the prior art hybrid packages. In addition, the prior art hybrid packages imposed the requirement on the I.C. chips that the thickness of such chips be maintained with tight tolerances to a predetermined value in order to reliably obtain good outer lead bonds. Since the active face of each chip with its I/O terminals to which the inner lead bond sites of the lead are bonded are exposed when the chips are mounted on a substrate, both the active face of the chips and their leads are subject to mechanical damage as well as to chemical attack or corrosion. Prior art packages of this type are also subject to edge shorts which occur if a lead touches the outer edge of the active face of an I.C. chip. It should also be noted that the bonds between inner lead bonding sites of the leads and the I/O terminals of the chips are physically weaker, i.e., they fail at lower tensile stresses than the bonds between the outer lead bonding sites of the leads and the I/O pads of the substrate.